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01/26/22

Cache/Fabric RTL and Microarchitecture Engineer

Tenstorrent

Minimum Qualifications

  • BS/MS/PhD in EE/ECE/CE/CS with at least 8 years of experience
  • Experience in Cache, Multi-processor coherency microarchitecure, familarity with AXI, TileLink and CHI protocol
  • Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
  • Expertise in logic design and ability to evaluate functional, performance, timing and power for you design

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CPU