Minimum Qualifications

• Define architecture and logic design requirements by understanding rapidly evolving AI/ML models; work with engineers across domains to understand real world use cases
• RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
• Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results

Location: Bangalore