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09/14/22

RISCV Debug and Trace Verification Engineer

Tenstorrent

Minimum Qualifications

  • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
  • Experience with Debug, Trace, JTAG and other design for debug (DFD) domains for an x86, ARM or RISCV based CPU
  • Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
  • Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools