Minimum Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience
• Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
• Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
• Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.