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IP

There is a desire among customers to own their silicon and tailor it to their specific use cases and needs, well beyond conventional AI training and inference and into automotive AI, high performance computing (HPC), and more.

Tenstorrent’s RISC-V-based Ascalon architecture has been developed with flexibility in mind, scalable from a massive, highly-performant 8-wide implementation down to a minimal 2-wide implementation, with multiple steps in between. The Tensix Cores that power our AI accelerators are equally scalable, designed to form a mesh that scales with as many cores as are needed.

RISC-V Processor Family
2-Wide Decode
3-Wide Decode
4-Wide Decode Sonic Boom
6-Wide Decode
8-Wide Decode
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2-Wide Decode
ideal Application:
Low-power, embedded systems, IoT devices, simple control applications
3-Wide Decode
ideal Application:
Higher-performance embedded systems, mobile devices, balance between power efficiency and performance
4-Wide Decode Sonic Boom
ideal Application:
General-purpose computing, higher-end embedded systems, laptops, entry-level servers
6-Wide Decode
ideal Application:
Workstations, high-end mobile devices, servers, high-performance computing tasks
8-Wide Decode
ideal Application:
High-end servers, data centers, scientific computing, large-scale virtualization, real-time data analytics
Features include:
RISC-V IP Optimized for Al: Designed specifically for advanced Al/ML workloads.
Silicon-Tested: Solutions have been validated on silicon for Al workload efficiency.
Adaptable Technology: Al technology platforms that are scalable and customizable.
Quick to Market: Al IP that enables swift and flexible integration for rapid deployment.
Power-Efficient: Delivers top-tier performance with minimal power consumption.

Have questions about Tenstorrent RISC-V IP?