TT-Ascalon
Ascalon represents the first generation of Tenstorrent's high-performance RISC-V CPU roadmap. It is more than just a processor; it's a testament to our dedication to advancing RISC-V technology and empowering the next era of high-performance computing. Designed by architects from industry leaders such as Apple, Tesla, Arm, and AMD, Ascalon is engineered to deliver unparalleled performance. With Ascalon, Tenstorrent is setting a new benchmark for the industry.
64-bit Out-of-Order Superscalar CPU
Tenstorrent’s Ascalon is a RVA23 compliant, 64-bit Out-of-Order Superscalar CPU offers the highest possible performance while maintaining area and power efficiency.
RVA 23 Compliant
Adherence to the latest RISC-V architecture specifications.
Advanced Branch Predictors
Enhancing speculative execution for increased performance.
256-bit Vector Data Path
Enabling high-speed parallel processing for demanding workloads.
High Performance Memory Sub-system
Optimized for rapid data access and efficient memory management.
Advanced Security, RAS, and Debug Features
Advanced Security, RAS, and Debug Features
Real world RISC-V
Ascalon’s emulation and validation stack lets you test real workloads before first silicon. It’s flexible enough for core/cache configs and robust enough for post-silicon debug.
Emulation
Test your workloads on Ascalon immediately, with flexible emulation support for multiple core and cache configurations and an open-source software toolchain ready to go.
Validation (Post-Silicon Ecosystem)
Ascalon's Design-for-Debug (DfD) tools streamline hardware bring-up, software development, and tuning, offering both standard and proprietary debugging features like Core Logic Analyzer and Debug Signal Trace.
Open Source, RISC-V Ready
Reference Models
APLIC
The APLIC is a stand-alone component of Whisper that models Advanced Platform-Level Interrupt Controller.
Whisper
Whisper is an open-source RISC-V instruction set simulator (ISS) that plays a crucial role in the verification of RISC-V cores. It also provides developers with the ability to run RISC-V code in an environment without the need for RISC-V hardware.
IOMMU
The IOMMU is a stand-alone component of Whisper that models the input-output memory management unit.
Riescue-C
Riescue-D
OCELOT
Yours Truly,
Get in touch with our IP team today to learn more about TT-Ascalon™, Tensix Neo, Open Chiplets, and more.