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Tenstorrent RISC-V

Tenstorrent RISC-V


Based on system PPA goal requirements, Ascalon RTL can be parameterized into a 6/4/3/2-wide superscalar O-o-O processor. The wide PPA range of TT CPU IP’s addresses the performance and power efficiency requirements from edge devices, edge servers, to Cloud servers.

  • Ascalon Specifications
    • 8-wide decode
    • 2 256-bit vector Units
    • 3 LD/ST with large load/store queues
    • 6 ALU/2 BR
    • 2 FPU Units
    • Ascalon Cluster
      • Aegis CPU: Ascalon-based Chiplet System Architecture
        • Companion CPU cluster for AI
        • Inter-cluster coherency
        • Directory-base coherency system
        • Large memory cache per DDR5-6400 channel
        • 4 cc-NUMA 32-core quadrants with hierarchical interconnection
        • Ample coherent/non-coherent bandwidth for system scalability

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