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Excited about the future of AI hardware? Apply to be a part of the Tenstorrent team >

Join Tenstorrent

We’re a startup, which means we’re all a little crazy. We are looking for flexible thinkers who are excited by the future of AI to join our team.

Tenstorrent is right for you if:

You are calm under pressure
You have a laid-back intensity
You love problem solving
You are focused and passionate
You want to build great products and have fun doing it

Our Offices

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

Our positions below will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

  • Architecture

Chip Security Architect

  • United States
  • Physical Design

CPU/AI Physical Design Block Lead

  • Santa Clara, California, United States
  • Architecture

CPU Architecture Engineering Manager

  • Tokyo, Japan
  • RISC-V

CPU Core Feature Verification and Debug Engineer

  • Bengaluru, Karnataka, India
  • RISC-V

CPU Core Feature Verification and Debug Engineer

  • Austin, Texas, United States
  • RISC-V

CPU Formal Verification Engineer

  • Austin, Texas, United States
  • RISC-V

CPU Load/Store Verification Engineer

  • Austin, Texas, United States
  • RISC-V

CPU Load/Store Verification Lead

  • Austin, Texas, United States
  • RISC-V

CPU Power Management Verification Engineer

  • Austin, Texas, United States
  • RISC-V

CPU RTL & Microarchitecture Engineer

  • Bengaluru, Karnataka, India
  • RISC-V

CPU RTL & Microarchitecture Engineer

  • Austin, Texas, United States
  • RISC-V

CPU Unit Verification Engineer

  • Santa Clara, California, United States
  • Architecture

Debug Architect

  • United States
  • RISC-V

Design Verification - CPU Subsystem

  • Bengaluru, Karnataka, India
  • RISC-V

Director, Design Verification Engineering

  • Santa Clara, California, United States
  • RISC-V

Director, Design Verification Engineering

  • Austin, Texas, United States
  • IP Product

Field Applications Engineer - IP

  • Santa Clara, California, United States
  • RISC-V

Frontend CAD Engineer

  • Austin, Texas, United States
  • RISC-V

Frontend CAD Engineer

  • Bengaluru, Karnataka, India
  • Pathfinding

GCC Compiler Engineer

  • Santa Clara, California, United States
  • Pathfinding

Kernel Developer

  • Bengaluru, Karnataka, India
  • Architecture

Performance Architect

  • United States
  • SoC & Digital Design

Principal Design Verification Engineer - Fabric and Memory Subsystem

  • Austin, Texas, United States
  • SoC & Digital Design

Principal DV Engineer – IO Memory Management Unit (IOMMU)

  • Austin, Texas, United States
  • SoC & Digital Design

Principal RTL Design Engineer - Fabric and Memory Subsystem

  • Austin, Texas, United States
  • SoC & Digital Design

Principal RTL Design Engineer - Security Subsystem

  • Austin, Texas, United States
  • Systems Engineering

Principal Systems Engineer

  • Santa Clara, California, United States
  • RISC-V

RTL Design Engineering Lead

  • Austin, Texas, United States
  • Customer Team

Senior Account Executive

  • Santa Clara, California, United States
  • IP Product

Senior IP Product Manager (CPU/Systems)

  • Santa Clara, California, United States
  • Physical Design

Senior Physical Design Engineer

  • Santa Clara, California, United States
  • Core Software & Compilers

Senior Software Engineer – Compilers

  • Toronto, Ontario, Canada
  • RISC-V

Shared Cache RTL Engineer

  • United States
  • SoC & Digital Design

Silicon IP Applications Engineer

  • Toronto, Ontario, Canada
  • IP Product

Software Functional Safety Manager

  • Taipei, Taiwan
  • Architecture

Sr. Principal High-Performance Computing Architect

  • Santa Clara, California, United States
  • Architecture

Sr. Principal High-Performance Computing SoC Architect

  • Austin, Texas, United States
  • Data Science and Engineering

Staff Data Engineer - Data Platform

  • Santa Clara, California, United States
  • Test & DFT

Staff Design for Test Engineer

  • Santa Clara, California, United States
  • SoC & Digital Design

Staff Digital Design Verification Engineer - Chiplets

  • Toronto, Ontario, Canada
  • RISC-V

Staff Emulation Methodology and Infrastructure Engineer

  • Austin, Texas, United States
  • Core Software & Compilers

Technical Program Manager - Software

  • Austin, Texas, United States