Unlock Your Architecture

RISC-V CPU

Tenstorrent builds on open source so you can own your architecture. RISC-V is an open ISA standard with no licensing fees or proprietary roadblocks.

The key to innovation is ownership without the obligation to stay with a single vendor. Having the freedom to choose means you can spend more time building products that move the industry forward.

Unlock Your Architecture

TT-Ascalon™

TT-Ascalon™ is built around open standards and designed to adapt to your needs.

  • Based on open RISC-V ISA
  • RVA23 compliant
  • Support for 2 to 8 cores per cluster
  • Configurable shared L2 cache
  • CHI.E and AXI5-LITE interface support
  • TrustZone-equivalent security solution based on RISC-V security primitives
  • Superior performance density
TT-Ascalon™

Industry-Leading 
Engineering

Tenstorrent’s RISC-V team is comprised of veteran silicon engineers from Intel, AMD, Tesla, and more. Our team has designed high-performance processor IP, and has consistently brought it to market in proven silicon.

Tenstorrent’s Vision
Industry-Leading 
Engineering
TT-Ascalon™ Performance Table
TT-Ascalon’s decode unit can scale from a compact and power efficient 2-wide implementation all the way up to a high-performance 8-wide solution.

Want to learn more about the TT-Ascalon™ RISC-V CPU IP?

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