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Tenstorrent Releases Open Source Beta of the Open Chiplet Atlas® (OCA) Harness

The OCA-compliant framework gives chiplet teams open, reusable infrastructure for security, boot, system management, debug and test, and die-to-die connectivity.

Oct 22, 2026

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Tenstorrent has released the open source beta of the Open Chiplet Atlas® (OCA) Harness. The Harness is a chiplet design framework that turns the OCA interoperability architecture into reusable, deployable implementations.

The OCA Specification defines the rules that let chiplets from different vendors work together across the software, system, protocol, transport, and physical layers. The OCA Harness builds those rules into the infrastructure every chiplet needs: security, boot, system management, debug and test, and die-to-die integration. Chiplet teams that use the Harness can lower non-recurring engineering (NRE) costs and integration risk, and spend more time on the application logic that sets their chiplet apart.

“The OCA architecture gives chiplet designers the freedom to build without depending on a single vendor,” said Wei-Han Lien, Chief CPU Architect and Senior Fellow at Tenstorrent. “The Harness gives teams a reference design that reduces integration complexity so they can focus on their core IP and launch custom silicon.”

The beta includes the complete Harness RTL and includes three management subsystems::

  • OCA Security Processor (SEP): serves as the chiplet’s root of trust, providing secure boot, measurement, key management, and lifecycle control.
  • OCA System Management Controller (SMC): manages system bring-up, clocks, power, thermal, reset coordination, and telemetry, and implements the OCA-defined boot and configuration protocols that peer chiplets use.
  • Debug and Test Ports (DTP): provide uniform cross-chiplet debug and test access, including JTAG and OCA cross-trigger support.

The OCA System Management Unit (SMU) brings these subsystems together, and the OCA AoU implementation carries native AXI4 traffic over UCIe die-to-die links between chiplets. A C++/SystemC virtual platform also lets teams start firmware development before RTL simulation or silicon.

BOS Semiconductors contributed the original AXI over UCIe RTL, and lowRISC helped open source the Harness.VNChip Labs and Signaloid are OCA ecosystem partners with contributions in progress.

“At VNChip Labs, we are proud to contribute to OCA and help make advanced chiplet design more open and accessible,” said Quang Le, Co-founder and CEO at VNChip Labs. “By providing a common, proven foundation, the OCA ecosystem can reduce development risk, accelerate time to silicon, and create a more level playing field for companies of all sizes.”

“Signaloid provides a compute accelerator for computing with probability distributions, enabling speedups by an order of magnitude. By removing integration friction, the OCA Harness allows our accelerator IP to tap seamlessly into a thriving and open chiplet ecosystem,” said Phillip Stanley-Marbell, CEO and Founder at Signaloid. “This makes it easy for us to integrate across a wide variety of complete systems and SiPs, with lower NRE costs and faster time-to-market.”

Tenstorrent designed the beta for early adopters, integrators, and contributors. The full release is targeted for January 2027.

Visit the OCA Harness GitHub repository to get started.